An instruction fetch unit of a microprocessor is responsible for continually providing the next appropriate instruction to an execution unit of the microprocessor. Generally, an instruction fetch unit computes a virtual address for the next instruction to be fetched, translates the virtual address to a physical address, retrieves an instruction corresponding to the physical address, and provides the instruction to the execution unit.
When multiple instruction sources such as an instruction cache and scratch pad are available, the instruction fetch unit may not be able to determine which instruction source to use to retrieve the desired instruction until the virtual address is translated into a physical address. Rather than waiting for the virtual address to be translated, a conventional instruction fetch unit may access all of the instruction sources simultaneously while the address is translated. After the address translation is completed, a conventional instruction fetch unit will inspect the retrieved instructions to determine if the desired instruction was retrieved by one of the instruction sources. If none of the instruction sources has retrieved the desired instruction, a conventional instruction fetch unit uses the translated address to target the appropriate instruction source to retrieve the desired instruction.
Although, accessing all the instruction sources simultaneously may reduce the time required to retrieve an instruction, it unnecessarily consumes a significant amount of the total power of a microprocessor. This makes microprocessors having conventional fetch units undesirable and/or impractical for many applications.
What is needed is a microprocessor that can access a variety of instruction sources while consuming less power than a microprocessor having a conventional fetch unit.